1. Field of the Invention
The present invention relates to a circuit and method for trimming integrated circuits, and more particularly, the present invention relates to a circuit and method for trimming packaged integrated circuits without requiring additional package pins or logic to accomplish same. Particular utility for the present invention is in trimming a reference voltage associated with a mixed-signal IC; although the present invention is equally applicable for any IC where a precise reference voltage is desired: for example, accurate voltage controlled oscillator, high precision DAC, accurate current generator, etc.
2. Description of Related Art
In manufacturing analog (mixed signal) integrated circuits, the basic building blocks are usually not accurately controlled by the manufacturing process as may be desired. For example, capacitors and resistors may have the wrong value, and MOS transistors may have the wrong gain setting. There are too many variables in the manufacturing process to yield absolute predictable results. Yet historically analog circuits often require very accurate voltage references, frequency references, and accurately ratioed elements.
To compensate for the process variability, many electronic circuits use analog trimming during test to set resistor values as necessary for proper operation of the circuit. A typical trimming technique utilizes a resistor ladder comprising a series of serially coupled resistors each in parallel with either a fuse or anti-fuse. A fuse is a device that is substantially an electrical short until it is blown open. An anti-fuse is an electrical open until blown when it becomes substantially an electrical short.
The fuse-blowing approach may take several forms, each with its own shortcomings. Laser fuses may be used directly across each resistor element in the ladder to enable and disable conduction through the resistor. During test, certain resistors are selected to open the shunt element thereby adding resistance to the serial path. The resistor ladder should be adjustable at wafer test over a range from say 10 to 2,560 ohms in 10 ohm increments.
The analog trimming may be performed iteratively, i.e. test, trim, test, trim, to measure the effect of the course trim and determine the necessary fine trimming. For iterative trimming, a laser trim system is typically installed on the wafer tester to alternately test and trim. However, one laser system per tester is very expensive. The laser is often in an idle state waiting for the tester. Moreover, if either the test system or laser breaks down both are inoperative.
An alternate approach is to use a zener anti-fuse across the resistor ladder. Such an element can be cheaply trimmed on the tester so that iterative testing can be done in one pass on the tester. Zener anti-fuses require large voltage to program. Such a voltage placed on the chip can affect the rest of IC especially for low voltage operation. Therefore, each anti-fuse requires its own external pad and probe card needle. This restricts the programming bit count to say 5-10 bits before the die area for test pads and complexity of the probe card requirements become prohibitive.
In general, iterative testing is a slow and expensive process. Consequently, many trimming techniques utilize only a single pass to evaluate which resistors in the serial string should be included to achieve the desired analog circuit operation. Thus, as result of a test measurement, the user blows the shunt fuse elements whereby the circuit is expected to operate as planned. The process of blowing the fuses typically involves laser trimming off-line from the test set to cut the poly material and open the shunt element. The circuit may be returned to the test set to verify proper trimming. If the subsequent testing should fail, the part is typically discarded since it is difficult to patch the shunt fuse elements.
Moreover, these processes are performed at a wafer level, i.e., before packaging of the IC and require probe cards, long cables, etc., which is a labor and time intensive task for each IC. During the packaging process (e.g., die, cut and ceramic or plastic encapsulation), the IC is subject to mechanical and chemical stress which can again alter the components that have been trimmed by the wafer trimming processes, rendering wafer-trimming an unattractive alternative. One partial resolution to wafer-level trimming procedures can be found in U.S. Pat. No. 5,079,516, issued to Russell et al. This patent discloses an after package (i.e., post-assembly) trimming circuit and method for a LF155 BIFET(copyright) monolithic JFET input operational amplifier, that operates to correct any discrepancies of a wafer trimming process performed before packaging of the IC. The type of JFET IC described in this patent includes balance package pins (38 and 39, FIG. 2) which are normally used to attach an external potentiometer to adjust the offset voltage after packaging. The ""516 proposes, however, the addition of on-chip trim circuitry which effects an internal trim procedure, utilizing the balance pins already provided. The ""516 also isolates the balance pins from the rest of the circuit after trimming, so that the trim value cannot be altered by an accidental input on the balance pins by the user. However, once trimmed the balance pins remain inactive, and cannot, by design be utilized by the IC. Thus, the balance pins remain as wasted real estate space on the IC, an important consideration when minimizing package pins and chip xe2x80x9creal estatexe2x80x9d. Additionally, newer JFET IC of the type described in the ""516 patent do not have external balance pins, and thus, cannot use the trim process proposed in the ""516, and must instead rely on wafer-level trimming processes. Thus, if the ""516 patent were to be modified with newer IC packages, the trim circuitry described therein would necessarily require additional package pins that would be only used for trimming.
Additionally, conventional trimming process using fuses and/or zener diode require significant input current to effectuate blowing the fuse or zapping the diode. It is recognized that the requirement of high current in an IC requires additional measures to ensure that other components remain isolated from high current conditions. Additionally, such high current places large power requirements on the IC, which is undesireable.
Therefore, there exists a need to provide an on-chip, after-package trim circuit which does not require additional external package pins can utilize package pins of the IC and which relinquishes the package pins after trimming, for use as proscribed by the IC. A need also exists to provide a trim circuit adapted to be isolated from the remainder of the IC, so that the functionality of the IC is not compromised and so that additional components need not be incorporated into the IC to effectuate the trim process. There also exists a need to provide a trim circuit and methodology that is dynamically designed, and insensitive to varying chip-to-chip tolerances of the components incorporated into the IC.
Accordingly, it is one object of the present invention to provide an after package integrated circuit trim circuit and method which utilizes fuses for setting a trim voltage.
It is another object of the present invention to provide an after package integrated circuit trim circuit and method which does not require additional pins to accomplish a trimming procedure.
The present invention accomplishes these and other objects by providing a programmable after-package, on-chip reference voltage trim circuit for an IC. The programmable trim circuit includes a register being controlled to generate a sequence of test bit signal and a sequence of set bit signals. A plurality of programmable trim cell circuits are selectively coupled to the register, and each cell receives a test bit signal and set bit signal from the register. The trim cells are adapted to generate output signals equal to said test bit signal or said set bit signal, respectively, supplied to each trim cell. A digital to analog converter (DAC) circuit is coupled to the output signals and generates a trim current signal proportional to the output signals. The trim current is injected into a resistor placed between trim current generator and voltage reference block. A trim voltage signal, with sign and magnitude is now available for adjusting the initial, fixed, voltage reference value. It is added to an initial value of a reference voltage generated by said IC.
In the preferred embodiment, the trim cell circuits include an OR gate having a first input and a second input, the second input being selectively coupled to said test bit signal. The trim circuits also include a set circuit portion including a first switch having a control node selectively coupled to the set bit signal and a conduction node, a second switch having a control node coupled to said conduction node of the first switch, an active node coupled to a common voltage rail supplied by said IC and a conduction node coupled to the first input of the OR gate. A nominal current source is provided in parallel with said second switch and connected to the first input of the OR gate and the voltage rail. A fuse is coupled between a ground potential rail supplied by the IC and the first input of the OR gate. The set bit signal controls the conduction state of the first and second switches, and the input value of the first input of the OR gate.
In operation, the preferred trim circuit operates as follows: if the set bit is high, both the first and second switches conduct and a conduction path between the voltage rail and ground is established through the fuse causing said fuse to break, and thus the voltage rail is permanently coupled to the first input of said OR gate; and if the set bit is low, both the first and second switches do not conduct and the fuse remains intact, and a conduction path is established between the voltage rail and ground through the fuse and the current source thereby generating a low input to the first input of the OR gate.
In method form, the present invention provides method of trimming a reference voltage for an integrated circuit comprising the steps of: measuring an initial value of a reference voltage signal generated by the IC; comparing the initial value signal to a high precision reference signal; generating a control signal indicative of the sign of difference between the initial value signal and the high precision signal; controlling a plurality of trim cell circuits to generate a bit sequence indicative of a sign and magnitude of a trim current; generating a trim current having a sign and value proportional to the bit sequence; generating a trim voltage by applying the trim current into a resistor placed between trim current generator and voltage reference block; adding the trim voltage to the initial value signal and determining if the added signals approximately equal the high precision reference signal; and permanently setting the bit values generated by the trim cells when the added signals equal the high precision reference signal. The preferred method also includes the step of electrically isolating the trim cells from the IC after the step of permanently setting said bit values.
It will be appreciated by those skilled in the art that although the following Detailed Description will proceed with reference being made to preferred embodiments and methods of use, the present invention is not intended to be limited to these preferred embodiments and methods of use. Rather, the present invention is of broad scope and is intended to be limited as only set forth in the accompanying claims.
Other features and advantages of the present invention will become apparent as the following Detailed Description proceeds, and upon reference to the Drawings, wherein like numerals depict like parts, and wherein: